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any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. overview the LC5822, lc5823, and lc5824 are cmos microcontrollers that feature the low-voltage operation required for battery-power applications and that provide 4 kb, 6 kb, or 8 kb of rom, 1 kilobit of ram, and an lcd driver. these microcontrollers support an instruction set based on that of the earlier lc5800, lc5812, and lc5814 for excellent efficiency in software development. applications lcd display in multi-function watches, timers, and other products control and lcd display in timers control and lcd display in miniature test equipment, health maintenance equipment, and other products these microcontrollers are optimal for products that include an lcd display, especially battery powered products. wide allowable operating ranges note * : when the backup flag is set, the bak pin is connected to v dd . features these microcontrollers are high-end versions of the lc5800 and provide the following features. low current drain * in halt mode (typical) ceramic oscillator 400 khz (3.0 v) 200 a crystal oscillator 32 khz (1.5 v, ag specifications) 3.0 a (lcd biases other than 1/3) 4.5 a (lcd drive: 1/3 bias) crystal oscillator 32 khz (3.0 v, li specifications) 2.0 a (lcd biases other than 1/3) 6.0 a (lcd drive: 1/3 bias) timer and counter functions one 8-bit programmable timer (may be used as an event counter) one 8-bit programmable reload timer time base timer (for clocks) watchdog timer 8-bit serial i/o (3-pin synchronous system) standby functions clock standby function (halt mode) only the oscillator circuits, the divider circuit, and the lcd driver operate. all other internal operations are stopped. this provides a power-saving function in which current drain is minimized, and allows a clock function to be implemented easily with low power dissipation. furthermore, low-speed and high-speed modes can be implemented by setting the operating modes of the two oscillator circuits. full standby function (hold mode) halt mode can be cleared by any of two external and two internal interrupts. cmos ic 82198rm (ot) no. 5944-1/24 sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 4-bit single-chip microcontrollers featuring 4 kb to 8 kb of rom, 1 kbit of ram, and an lcd driver for medium speed small-scale control applications lc5824, lc5823, LC5822 ordering number : en5944 power cycle supply options times voltage notes supply range ext-v 10 s v dd = 2.3 to 3.6 v when an 800-khz ceramic oscillator is used ext-v 20 s v dd = 2.3 to 3.6 v when an 400-khz ceramic oscillator is used ext-v 61 s v dd = 2.3 to 3.6 v when an 65-khz crystal oscillator is used ext-v 122 s v dd = 2.0 to 3.6 v when an 32-khz crystal oscillator is used li 122 s v dd = 2.6 to 3.6 v * when an 32-khz crystal oscillator is used ag 122 s v dd = 1.3 to 1.65 v when an 32-khz crystal oscillator is used
improved i/o functions external interrupt pins input pins that can clear halt mode: 10 pins (maximum) input ports with input resistors that can be controlled from software: 8 pins (maximum) pins with a function that prevents the input port floating state: 8 pins (maximum) lcd drive pins: 4 pins (common), 42 pins (segment outputs) general-purpose i/o ports: 16 pins (when all 4 p port pins are used) general-purpose inputs: 8 pins general-purpose outputs (1): 1 pin (the alm pin) general-purpose outputs (2): 42 pins (when all 42 of the lcd segment outputs are switched over to function as general-purpose outputs) 8-bit serial output port: 1 set (3 pins: output, input, and clock) functional overview program rom: 4096 16 bits lc5824 3072 16 bits lc5823 2048 16 bits LC5822 internal ram: 256 4 bits all instructions execute in a single cycle. extensive set of interrupt functions for clearing halt and hold mode 8 halt mode clearing functions 5 hold mode clearing functions 6 interrupt functions subroutines can be nested up to 8 levels (special- purpose registers that are shared with the interrupt function are built in.) powerful hardware to increase system processing capacity segment port related hardware built-in segment pla circuit built-in segment decoder support for six different lcd drive specifications outputs can be switched to cmos levels built-in 8-bit synchronous serial i/o circuit 8-bit read/write timer (plus a separate 8-bit prescaler; can be used as and event counter) 8-bit reload timer (plus built-in 8-bit prescaler) built-in 8-bit prescaler (for use with timer 1, timer 2, and the serial counter) all of ram can be used a working area (ram bank system) dedicated data pointer register for ram access 15-stage divider circuit for clocks (also used as the lcd voltage alternation frequency generator) 8-bit table reference function (reads 8-bit rom data) chattering prevention circuit (on two ports) alarm signal generation circuit lcd panel drive output pins with high flexibility (42 pins) the lcd output pins can be switched to function as general-purpose outputs. cmos/p-channel/n-channel type combinations: up to 42 pins an alternation frequency appropriate for the lcd panel used can be selected. an oscillator appropriate for your system? specifications can be selected. a 32- or 65-khz crystal oscillator can be selected (used when a clock function is required or for low current drain operation.) a ceramic oscillator with a frequency from 400 khz to 2 mhz can be selected (when high-speed operation is required.) available delivery formats: qip-80 and chip package dimensions unit: mm 3174-qfp80e no. 5944- 2 /24 lc5824, lc5823, LC5822 drive system number of driven segments required number of common pins bias ?duty 168 segments 4 pins bias ?duty 126 segments 3 pins bias ?duty 168 segments 4 pins bias ?duty 126 segments 3 pins bias ?duty 84 segments 2 pins static drive 42 segments 1 pin [lc5824, 5823, 5822] sanyo: qip80e
pin assignment no. 5944- 3 /24 lc5824, lc5823, LC5822 top view
no. 5944- 4 /24 lc5824, lc5823, LC5822 pad arrangement chip size: 4.92 mm 5.15 mm pad size: 120 m 120 m chip thickness 480 m (chip specifications) pad coordinates pad no. pin coordinates x m y m 60 seg 22 ?030 ?178 61 seg 23 ?850 ?178 62 seg 24 ?670 ?178 63 seg 25 ?490 ?178 64 seg 26 ?310 ?178 65 seg 27 ?130 ?178 66 seg 28 ?50 ?178 67 seg 29 ?70 ?178 68 seg 30 ?90 ?178 69 seg 31 ?10 ?178 70 seg 32 ?30 ?178 71 seg 33 ?0 ?178 72 seg 34 122 ?178 73 seg 35 302 ?178 74 seg 36 482 ?178 75 seg 37 662 ?178 76 seg 38 842 ?178 77 seg 39 1022 ?178 78 seg 40 1202 ?178 79 seg 41 1382 ?178 80 seg 42 1562 ?178 81 xc 1774 ?178 82 xtout 1954 ?178 83 xtin 2134 ?178 1 v dd 2257 ?959 2 v ss 2257 ?779 3 cfin/p1 2257 ?599 4 cfout/p2 2257 ?402 pad no. pin coordinates x m y m 5 v dd 3 2257 ?212 6 v dd 2/bak 2257 ?032 7 v dd 1 2257 ?52 8 alm 2257 ?01 9 so1 2257 ?19 10 so2 i/o port 2257 ?36 11 so3 i/o port 2257 56 12 so4 i/o port 2257 132 13 m1 2257 364 14 m2 i/o port 2257 544 15 m3 i/o port 2257 724 16 m4 i/o port 2257 904 17 res i/o port 2257 1636 18 test 2330 1998 19 test 2330 2178 20 tst 2150 2178 21 cup1 1970 2178 22 cup2 1790 2178 23 seg 1 1606 2178 24 seg 2 1426 2178 25 seg 3 1246 2178 26 seg 4 1066 2178 27 seg 5 886 2178 28 seg 6 706 2178 29 seg 7 526 2178 30 seg 8 346 2178 31 seg 9 166 2178 32 seg 10 ?4 2178 pad no. pin coordinates x m y m 33 seg 11 ?94 2178 34 seg 12 ?74 2178 35 seg 13 ?46 2178 36 seg 14 ?26 2178 37 seg 15 ?06 2178 38 seg 16 ?086 2178 39 seg 17 ?266 2178 40 seg 18 ?446 2178 41 seg 19 ?626 2178 42 seg 20 ?806 2178 43 seg 21 ?986 2178 44 com1 ?270 1871 45 com2 ?270 1628 46 s1 ?270 1367 47 s2 input port ?270 1140 48 s3 input port ?270 960 49 s4 input port ?270 734 50 k1 ?270 328 51 k2 input port ?270 88 52 k3 input port ?270 ?40 53 k4 input port ?270 ?80 54 a1 ?270 ?93 55 a2 i/o ports ?270 ?73 56 a3 i/o ports ?270 ?53 57 a4 i/o ports ?270 ?133 58 com3/p3 ?270 ?602 59 com4/p4 ?270 ?846 note: the pin numbers are the qip-80e mass-production package pin numbers. the test pin (tst) must be connected to v ss . pads number 42 and 43 in the chip version must be left open. do not use solder dip techniques to mount the qip-80e package version. in the chip version, the substrate must be either connected to v ss or left open.
system block diagram no. 5944- 5 /24 lc5824, lc5823, LC5822 ram: data memory rom: program memory dp: data pointer register bnk: bank register apg: ram page flag ac: accumulator alu: arithmetic and logic unit b: b register opg: rom page flag pc: program counter ir: instruction register sts1: status register 1 sts2: status register 2 sts3: status register 3 sts4: status register 4 pla: programmed logic array used for segment data and strobe functions wait.c: wait time counter address buffer accumulator (ac) (4 bits) data i/o - d bus timer 1 timer 2 carrier control circuit interrupt control watchdog timer lcd driver reset circuit chronograph circuit chronograph control circuit switch- ing circuit system clock generator voltage step- serial i/o b register (4 bits) opg (2 bits) program counter (13 bits) clock timer (15 bits) alarm tone generator segment decoder strobe decoder table reference crystal oscillator circuit (32 khz/65 khz) cf/rc oscillator circuit (400 khz to 4 mhz)
no. 5944- 6 /24 lc5824, lc5823, LC5822 pin functions pin no. pin i/o function options status at reset 24 25 v dd v ss 30 29 28 v dd 1 v dd 2/bak v dd 3 lcd drive power supply power supply pin ag specifications li specifications ext-v specifications 42 43 cup1 cup2 connections of the lcd power supply step-up (step-down) capacitors 26 27 cfin cfout input output system clock oscillator connections ceramic element connections (cf specifications) rc component connections (rc specifications) * : this oscillator circuit is stopped when a stop or slow instruction is executed. cf specifications rc specifications unused 23 22 xtin xtout input output used for reference counting (clock specifications, lcd alternation frequency) and as the system clock. 32-khz crystal oscillator 65-khz crystal oscillator * : this oscillator circuit is stopped when a stop instruction is executed. 32-khz specifications 65-khz specifications 38-khz specifications unused xc used for the phase compensation capacitor connected between this pin and xtout and xtin. this pin is only used in the chip product. 67 68 69 70 s1 s2 s3 s4 input input-only port input pins used to acquire input data to ram 1.95-ms and 7.8-ms chattering exclusion circuits included. pull-down resistors are built in. note: the 1.95 ms and 7.8 ms values are for a ? of 32.768 khz. presence or absence of low-level hold transistors pull-down resistors enabled note: after a reset is cleared, these pins go to the floating state. 71 72 73 74 k1 k2 k3 k4 input input-only port input pins used to acquire input data to ram 1.95-ms and 7.8-ms chattering exclusion circuits included. pull-down resistors are built in. note: the 1.95 ms and 7.8 ms values are for a ? of 32.768 khz. presence or absence of low-level hold transistors pull-down resistors enabled note: after a reset is cleared, these pins go to the floating state. 36 37 38 39 m1 m2 m3 m4 i/o i/o port input pins used to acquire input data to ram. output pins used to output ram data. m4 is also used as the tm1 external clock input in tm1 mode 3. m3 is also used for hef8 halt mode clear control. * : the minimum period for clock signal inputs is twice the cycle time ?pull-down resistors are built in. presence or absence of low-level hold transistors output type: cmos or p-channel pull-down resistors enabled note: after a reset is cleared, these pins go to the floating state. input mode the output latch data is set to 1. 26 27 79 80 p1 p2 p3 p4 i/o i/o port input pins used to acquire input data to ram. output pins used to output ram data. pull-down resistors are built in. the same as those for m1 to m4. however, only for valid ports. the same as those for m1 to m4. however, only for valid ports. 76 77 78 79 a1 a2 a3 a4 i/o i/o port input pins used to acquire input data to ram. output pins used to output ram data. pull-down resistors are built in. a1 is also used as the external interrupt request control input signal (int). the same as those for m1 to m4. the same as those for m1 to m4. continued on next page. power supply specifications
no. 5944- 7 /24 lc5824, lc5823, LC5822 continued from preceding page. pin no. pin i/o function options status at reset 32 33 34 35 so1 so2 so3 so4 i/o i/o port input pins used to acquire input data to ram. output pins used to output ram data. pull-down resistors are built in. so1 to so3 are also used as the serial interface pins. the serial interface function can be selected under program control. pin functions: so1: serial input so2: serial output so3: serial clock the serial clock can be taken from either internal or external sources, and can be set up to detect either rising or falling edges under program control. identical to m1 through m4 identical to m1 through m4 31 alm output output-only pin a signal modulated by ?, ?, or ? can be output under program control. low-level output 40 res input ic internal reset input the program counter is set to point to location 00h. the reset input level can be set to be either high or low. either a pull-up or a pull-down resistor is built in. note: applications must apply the reset signal level for at least 500 s to effect a reset. selection of a pull-up or pull-down resistor selection of active-low or active-high reset logic 44 64 1 21 seg 22 seg 21 seg 22 seg 42 output lcd panel drive outputs/general-purpose outputs lcd panel drive (1) static (2) 1/2 bias 1/2 duty (3) 1/2 bias 1/3 duty (4) 1/2 bias 1/4 duty (5) 1/3 bias 1/3 duty (6) 1/3 bias 1/4 duty one of items (1) through (5) is selected as a mask option. general-purpose output ports (1) cmos output (2) p-channel open-drain output (3) n-channel open-drain output one of items (1) through (3) is selected as a mask option. the adoption of the segment pla in these microcontrollers means that there is no need for programs to control the lcd/general-purpose output states of these pins. output latch control is supported in the oscillator stopped standby states and during a reset. any combination of lcd and general-purpose output functions may be used. switching between lcd drive output and general-purpose output switching between the lcd drive type options static 1/2 bias 1/2 duty 1/2 bias 1/3 duty 1/2 bias 1/4 duty 1/3 bias 1/3 duty 1/3 bias 1/4 duty general-purpose output type switching cmos p-channel open-drain n-channel open-drain standby mode output latch control when used for lcd drive: all lit all off * determined by the master options when used as general- purpose outputs: high level low level * determined by the master options note: when a combination of lcd drive and general-purpose outputs is selected, these pins will be either: all lit/high-level output, or all off/low-level output. during the reset period, the lcd drive functions as static drive. 65 66 79 80 com1 com2 com3 com4 output common drive outputs for the lcd panel the table below lists which pins are used in each of the drive types. however, note that the listed alternation frequencies are the typical specifications when ? is 32.768 khz. 41 tst input test input in the qip-80 version, this pin must be connected to v ss . in the chip version, this pin must be left open or connected to v ss . test test test pins. (these are not used in the device user interface.) note: note that the 5 ?symbol indicates that the corresponding common pin cannot be used in that drive type. * in products with the cf specifications, the alternation frequency signal stops briefly. static 1/2 duty 1/3 duty 1/4/duty com1 l l l l l l l l com2 5 l l l l l l com3 5 5 l l l l com4 5 5 5 l l alternation 32 hz 32 hz 42.7 hz 64 hz frequency
no. 5944- 8 /24 lc5824, lc5823, LC5822 sample application circuit lcd : 1/2 bias ?1/4 duty
no. 5944- 9 /24 lc5824, lc5823, LC5822 oscillator circuit options option circuit type notes the cycle time is 4 times the f1 period. the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive waveform generation clock, and for s/k port chattering prevention. osc1 is stopped by the execution of a slow instruction. rc & xtal the cycle time is 4 times n times the f1 period. (n:1) the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive waveform generation clock, and for s/k port chattering prevention. osc1 is stopped by the execution of a slow instruction. cf & xtal ?400 khz (cf) ?4 mhz (cf) the cycle time is 4 times the f1 period. the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive waveform generation clock, and for s/k port chattering prevention. rc timing generator divider timing generator divider timing generator divider continued on next page.
no. 5944- 10 /24 lc5824, lc5823, LC5822 option circuit type notes the cycle time is 4 times n times the f1 period. (n:1) the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive frequency generation clock, and for s/k port chattering prevention. cf ?400 khz ?4 mhz the cycle time is 4 times the f2 period. the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive waveform generation clock, and for s/k port chattering prevention. note that the cfin and cfout pins are switched over to function as the p1 and p2 pins. xtal ?32 khz ?55 khz continued from preceding page. timing generator divider timing generator divider
no. 5944- 11 /24 lc5824, lc5823, LC5822 crystal oscillator circuit options option circuit type notes the resistor rd is built into the ic when this circuit is used at 32 khz. used at 32 khz the cycle time is 4 times n times the f1 period. (n:2) the divider circuit outputs (? through ?5) are used as the clock time base, the lcd drive frequency generation clock, and for s/k port chattering prevention. osc1 is stopped by the execution of a slow instruction. used at 38 khz used at 65 khz input port options option circuit type notes when use of the hold transistor is selected, it is used to minimize the current drain that flows in the pull-down resistor when a push- button switch is used with s1 or a slide switch is used with s2. when the input open specifications are selected, before reading the input, the pull- down transistor is turned on. then the input state is read and the pull-down transistor is turned off. if the input was in the floating state, the low level hold transistor operates to hold the level. if use of the hold transistor is not selected: the circuit is used with the pull-down transistor turned on. select unused if the external control signal line connected to this input will never be in the floating state. low level hold transistor selection res pin option circuit type notes internal resistor and polarity selections reset on low, pull-up resistor included reset on high, pull-down resistor included reset on low, no resistors connected reset on high, no resistors connected pull-up resistor, pull-down resistor, resistors left open, and level selections bus sf2/rf2, d2 to d7 output mode pull-down resistor pull-down resistor pull-up resistor low level hold transistor
mask option list voltage specifications ag specifications li specifications ext-v specifications lcd driver static 1/2 bias ?1/2 duty ? 1/2 bias ?1/3 duty ? 1/2 bias ?1/4 duty ? 1/3 bias ?1/3 duty ? 1/3 bias ?1/4 duty ? unused segment port states during a reset lcd driver pins ? all lit ? all off cmos p/n-channel pins ? high level ? low level oscillator specifications cf only (ceramic oscillator element) rc only (using a resistor and a capacitor) crystal only cf + crystal rc + crystal cf 400 khz 800 khz 1 mhz 2 mhz 4 mhz rc 400 khz 800 khz 1 mhz crystal 32 khz 65 khz 38 khz lcd alternation frequency slow typ fast external reset circuit res pin res pin + s1 to s4 pressed at the same time internal reset circuit (power on reset) selected disabled res pin reset on low, pull-up resistor included reset on high, pull-down resistor included reset on low, no resistors connected reset on high, no resistors connected alarm output initial level low level high level chronometer and strobe selection 00h 10h 00h & 10h unused port s low level hold transistors low level hold transistors present low level hold transistors disabled port k low level hold transistors low level hold transistors present low level hold transistors disabled port m low level hold transistors low level hold transistors present low level hold transistors disabled port p low level hold transistors low level hold transistors present low level hold transistors disabled port so low level hold transistors low level hold transistors present low level hold transistors disabled port a low level hold transistors low level hold transistors present low level hold transistors disabled m1 to m4 outputs cmos p-channel n-channel p1 to p4 outputs cmos p-channel n-channel a1 to a4 outputs cmos p-channel n-channel no. 5944- 12 /24 lc5824, lc5823, LC5822
these electrical characteristics are provisional and the values are subject to change. ag specifications no. 5944- 13 /24 lc5824, lc5823, LC5822 parameter symbol conditions and applicable pins ratings unit min typ max v dd ?.3 +4.0 v v dd 1 ?.3 +4.0 v maximum supply voltage v dd 2 ?.3 +5.5 v v dd 3 for 1/3-bias lcd drive techniques ?.3 +4.0 v v dd 3 for lcd drive techniques other than 1/3 bias ?.3 +4.0 v s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, maximum input voltage v in 1 res,tst ?.3 v dd + 0.3 v m1 to m4, a1 to a4, so1 to so4, alm, cup2 v out 1 (with m1 to m4, a1 to a4, and so1 to so4 in input mode) ?.3 +0.3 v maximum output voltage v out 2 segout, com1 to com4, cup1 ?.3 v dd 3 + 0.3 v operating temperature topg ?0 +65 c storage temperature tstg ?0 +125 c absolute maximum ratings at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max v dd vbak = v dd 1 1.3 1.65 v v dd 1 supply voltage v dd 2 2.4 3.3 v v dd 3 for 1/3-bias lcd drive techniques 3.7 4.95 v v dd 3 for lcd drive techniques other than 1/3 bias 2.4 3.3 s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, high-level input voltage v ih (with m1 to m4, a1 to a4, and so1 to so4 in input mode) v dd ?0.2 v dd v res s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, low-level input voltage v il (with m1 to m4, a1 to a4, and so1 to so4 in input mode) 0 0.2 v res operating frequency fopg ta = ?0 to +65 c 32 33 khz allowable operating ranges at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max r in 1a v dd = 1.5 v, low level hold transistor 50 500 k v in = 0.35 v dd * 1 figure 1 r in 1b v dd = 1.5 v, programmable pull-down resistor 50 1000 k v in = 0.7 v dd * 1 figure 1 input resistance r in 2a v dd = 1.5 v, low level hold transistor 50 500 k v in = 0.35 v dd , input mode * 2, figure 1 r in 2b v dd = 1.5 v, programmable pull-down resistor 50 1000 k v in = 0.7 v dd , input mode * 2, figure 1 r in 3 v dd = 1.5 v, the res pin pull-up/pull-down resistor 10 300 k v in = 0.7 v dd /0.3 v dd high-level output voltage v oh 1 v dd = 1.3 v, i oh = ?50 a, alm v dd ?0.65 v low-level output voltage v ol 1 v dd = 1.3 v, i ol = 250 a, alm 0.65 v v dd = 1.5 v, m1 to 4, a1 to 4, so1 to 4 high-level output voltage v oh 2 i oh = ?0 a, v dd ?0.2 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) v dd = 1.5 v, m1 to 4, a1 to 4, so1 to 4 low-level output voltage v ol 2 i ol = 20 a, 0.2 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) electrical characteristics at ta = 25 c 2 c, v ss = 0 v, v dd = v dd 1 continued on next page.
no. 5944- 14 /24 lc5824, lc5823, LC5822 continued from preceding page. parameter symbol conditions and applicable pins ratings unit min typ max segment driver output impedance [when set up as cmos output ports] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ? a, segment 1 to 42 v dd ?1.0 v low-level output voltage v ol 3 v dd = 1.5 v, i ol = 3 a, segment 1 to 42 1.0 v [when set up as p-channel open-drain output ports] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ? a, segment 1 to 42 0.3 1.0 v output off leakage current i off v dd = 1.5 v, v ol = v ss , segment 1 to 42 1.0 a [static drive] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ?.4 a, segout v dd 2 ?0.2 v low-level output voltage v ol 3 v dd = 1.5 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 1.5 v, i oh = ? a, com1 v dd 2 ?0.2 v low-level output voltage v ol 4 v dd = 1.5 v, i ol = 4 a, com1 0.2 v [duplex drive (1/2 bias - 1/2 duty)] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ?.4 a, segout v dd 2 ?0.2 v low-level output voltage v ol 3 v dd = 1.5 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 1.5 v, i oh = ? a, com1 to com2 v dd 2 ?0.2 v middle-level output voltage v om v dd = 1.5 v, i oh = ? a, i ol = 4 a, com1 to com2 v dd 1 ?0.2 v dd 1 + 0.2 v low-level output voltage v ol 4 v dd = 1.5 v, i ol = 4 a, com1 to com2 0.2 v [1/2 bias - 1/3 duty and 1/2 bias - 1/4 duty drive] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ?.4 a, segout v dd 2 ?0.2 v low-level output voltage v ol 3 v dd = 1.5 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 1.5 v, i oh = ? a, com1 to com3 (1/3 duty) v dd 2 ?0.2 v com1 to com4 (1/4 duty) middle-level output voltage v om v dd = 1.5 v, i oh = ? a, i ol = 4 a, v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com3 (1/3 duty), com1 to com4 (1/4 duty) low-level output voltage v ol 4 v dd = 1.5 v, i ol = 4 a, com1 to 2 0.2 v com1 to com3 (1/3 duty), com1 to com4 (1/4 duty) [1/3 bias - 1/3 duty and 1/3 bias - 1/4 duty drive] high-level output voltage v oh 3 v dd = 1.5 v, i oh = ?.4 a, segout v dd 3 ?0.2 v m1-level output voltage v om 1? v dd = 1.5 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 2 ?0.2 v dd 2 + 0.2 v m2-level output voltage v om 2? v dd = 1.5 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 1 ?0.2 v dd 1 + 0.2 v low-level output voltage v ol 3 v dd = 1.5 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 1.5 v, i oh = ? a, com1 to com3 (1/3 duty) v dd 3 ?0.2 v com1 to com4 (1/4 duty) m1-level output voltage v om 1? v dd = 1.5 v, i oh = ? a, i ol = 4 a, v dd 2 ?0.2 v dd 2 + 0.2 v com1 to com3 (1/3 duty), com1 to com4 (1/4 duty) m2-level output voltage v om 2? v dd = 1.5 v, i oh = ? a, i ol = 4 a, v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com3 (1/3 duty), com1 to com4 (1/4 duty) low-level output voltage v ol 4 v dd = 1.5 v, i ol = 4 a, com1 to com3 (1/3 duty), 0.2 v com1 to com4 (1/4 duty) continued on next page.
no. 5944- 15 /24 lc5824, lc5823, LC5822 continued from preceding page. parameter symbol conditions and applicable pins ratings unit min typ max [output voltage] lcd drive method: 1/3 bias (doubler) v dd 2 v dd = 1.35 v, fopg = 32.768 khz, c1 to c3 = 0.1 f 2.5 v figure 2 (tripler) v dd 3 v dd = 1.35 v, fopg = 32.768 khz, c1 to c3 = 0.1 f 3.75 v figure 2 lcd drive method: 1/2 bias (doubler) v dd 2 v dd = 1.35 v, fopg = 32.768 khz, c1 to c2 = 0.1 f 2.5 v figure 3 [current drain (with the backup flag cleared)] lcd drive method: 1/3 bias | i dd | v dd = 1.5 v, in halt mode, c1 to c3 = 0.1 f, ci = 25 k , 3.5 a figure 2, co = cg = 20 pf, 32.768 khz xtal lcd drive methods other than | i dd | v dd = 1.5 v, in halt mode, c1 = c2 = 0.1 f, ci = 25 k , 2.0 a 1/3 bias figure 3, co = cg = 20 pf, 32.768 khz xtal oscillator start voltage | vstt | co = cg = 20 pf, ci = 25 k , figure 3, 1.35 v 32.768 khz xtal oscillator hold voltage | v hold | v bak = v dd 1, ci = 25 k , figures 2 and 3 1.3 1.65 v co = cg = 20 pf, 32.768 khz xtal oscillator start time tstt v dd = 1.35 v, ci = 25 k , figure 4, 10 sec co = cg = 20 pf, 32.768 khz xtal oscillator correction capacitance 10p xc 8 10 12 pf 20p xtout 16 20 24 pf
no. 5944- 16 /24 lc5824, lc5823, LC5822 li specifications absolute maximum ratings at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max v dd ?.3 +4.0 v v dd 1 v bak = v dd 1 or v dd 2 ?.3 +4.0 v maximum supply voltage v dd 2 ?.3 +4.0 v v dd 3 (lcd drive method: 1/3 bias) ?.3 +5.5 v v dd 3 (lcd drive methods other than 1/3 bias) ?.3 +4.0 v maximum input voltage s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, v in 1 (with m1 to m4, a1 to a4, and so1 to so4 in input mode) ?.3 v dd + 0.3 v res, tst maximum output voltage v out 1 m1 to m4, a1 to a4, so1 to so4, (lcd drive method: 1/3 b ias) (with m1 to m4, a1 to a4, and so1 to so4 in output mode) ?.3 v dd + 0.3 v alm, cup2 v out 2 segout, com1 to com4, cup1 ?.3 v dd 3 + 0.3 v (lcd drive methods other than m1 to m4, a1 to a4, so1 to so4, 1/3 bias) v out 2 (with m1 to m4, a1 to a4, and so1 to so4 in output mode) ?.3 v dd + 0.3 v alm, segout, com1 to com4, cup1, cup2 operating temperature topg ?0 +65 c storage temperature tstg ?0 +125 c parameter symbol conditions and applicable pins ratings unit min typ max v dd v bak = v dd /2 2.0 3.6 v v dd 2 (with the backup flag cleared) supply voltage v dd v bak = v dd 1.3 3.6 v v dd 2 (with the backup flag uncleared) v dd 3 (lcd drive method: 1/3-bias) 3.9 5.0 v v dd 3 (lcd drive methods other than 1/3 bias) v dd 3 = v dd 2 v s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, high-level input voltage v ih (with m1 to m4, a1 to a4, and so1 to so4 in input mode) v dd ?0.4 v dd v res s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, low-level input voltage v il (with m1 to m4, a1 to a4, and so1 to so4 in input mode) 0 0.4 v res operating frequency fopg ta = ?0 to +65 c 32 33 khz allowable operating ranges at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max r in 1a v dd = 3.0 v, v in = 0.35 v dd 50 500 k low level hold transistor * 1, figure 5 r in 1b v dd = 3.0 v, v in = 0.7v dd 50 1000 k programmable pull-down resistor * 1, figure 5 input resistance r in 2a v dd = 3.0 v, input mode, low level hold transistor * 1, 50 500 k v in = 0.35 v dd , figure 5 r in 2b v dd = 3.0 v, programmable pull-down resistor, * 2, 50 1000 k v in = 0.7 v dd , input mode, figure 5 r in 3 v dd = 3.0 v, res pin pull-up/pull-down resistor 10 300 k v in = 0.7 v dd /0.3 v dd electrical characteristics at ta = 25 c 2 c, v ss = 0 v, v dd = v dd 2
no. 5944- 17 /24 lc5824, lc5823, LC5822 parameter symbol conditions and applicable pins ratings unit min typ max high-level output voltage v oh 1 v dd = 2.5 v, i oh = ?50 a, alm v dd ?0.65 v low-level output voltage v ol 1 v dd = 2.5 v, i ol = 250 a, alm 0.65 v high-level output voltage v oh 2 v dd = 3.0 v, i oh = ?0 a, m1 to m4, a1 to a4, so1 to so4, v dd ?0.4 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) low-level output voltage v ol 2 v dd = 3.0 v, i ol = 40 a, m1 to m4, a1 to a4, so1 to so4, 0.4 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) segment driver output impedance [when set up as cmos output ports] high-level output voltage v oh 3 v dd = 3.0 v, i oh = ? a, segment 1 to 42 v dd ?1 v low-level output voltage v ol 3 v dd = 3.0 v, i ol = 5 a, segment 1 to 42 1 v [when set up as p-channel open-drain output ports] high-level output voltage v oh 3 v dd = 2.5 v, i oh = ?0 a, segment 1 to 42 0.3 1 v output off leakage current i off v dd = 3.0 v, v ol = v ss 1 a [static drive] high-level output voltage v oh 3 v dd = 3.0 v, i oh = ?.4 a, segout v dd ?0.2 v low-level output voltage v ol 3 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 3.0 v, i oh = ? a, com1 v dd ?0.2 v low-level output voltage v ol 4 v dd = 3.0 v, i ol = 4 a, com1 0.2 v [duplex drive (1/2 bias - 1/2 duty)] high-level output voltage v oh 3 v dd = 3.0 v, i oh = ?.4 a, segout v dd ?0.2 v low-level output voltage v ol 3 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 3.0 v, i oh = ? a, com1 to com2 v dd ?0.2 v middle-level output voltage v om v dd = 3.0 v, i oh = ? a, i ol = 4 a, com1 to com2 v dd 1 ?0.2 v dd 1 + 0.2 v low-level output voltage v ol 4 v dd = 3.0 v, i ol = 4 a, com1 to com2 0.2 v [1/2 bias - 1/3 duty and 1/2 bias - 1/4 duty drive] high-level output voltage v oh 3 v dd = 3.0 v, i oh = ?.4 a, segout v dd ?0.2 v low-level output voltage v ol 3 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 4 v dd = 3.0 v, i oh = ? a, com1 to com3 (1/3 duty) v dd ?0.2 v com1 to com4 (1/4 duty) v dd = 3.0 v, i oh = ? a, i ol = 4 a, middle-level output voltage v om com1 to com3 (1/3 duty) v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com4 (1/4 duty) low-level output voltage v ol 4 v dd = 3.0 v, i ol = 4 a, com1 to com3 (1/3 duty) 0.2 v com1 to com4 (1/4 duty) electrical characteristics at ta = 25 c 2 c, v ss = 0 v, v dd = v dd 2 continued on next page.
no. 5944- 18 /24 lc5824, lc5823, LC5822 continued from preceding page. parameter symbol conditions and applicable pins ratings unit min typ max [1/3 bias - 1/3 duty and 1/3 bias - 1/4 duty drive] high-level output voltage v oh 3 v dd = 3.0 v, i oh = ?.4 a, segout v dd 3 ?0.2 v m1-level output voltage v om 1? v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 2 ?0.2 v dd 2 + 0.2 v m2-level output voltage v om 2? v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 1 ?0.2 v dd 1 + 0.2 v low-level output voltage v ol 3 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v v dd = 3.0 v, i oh = ? a, high-level output voltage v oh 4 com1 to com3 (in 1/3 duty mode) v dd 3 ?0.2 v com1 to com4 (in 1/4 duty mode) v dd = 3.0 v, i oh = ? a, i ol = 4 a, m1-level output voltage v oh 1? com1 to com3 (in 1/3 duty mode) v dd 2 ?0.2 v dd 2 + 0.2 v com1 to com4 (in 1/4 duty mode) v dd = 3.0 v, i oh = ? a, i ol = 4 a, m2-level output voltage v om 2? com1 to com3 (in 1/3 duty mode) v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com4 (in 1/4 duty mode) v dd = 3.0 v, i ol = 4 a, low-level output voltage v ol 4 com1 to com3 (in 1/3 duty mode) 0.2 v com1 to com4 (in 1/4 duty mode) [output voltage] lcd drive method: 1/3 bias (halver) v dd 1 v dd = 3.0 v, fopg = 32.768 khz, 1.35 v c1 to c4 = 0.1 f, figure 6 (tripler) v dd 3 v dd = 3.0 v, fopg = 32.768 khz, 4.1 v c1 to c4 = 0.1 f, figure 6 lcd drive method: 1/2 bias (halver) v dd 1 v dd = 3.0 v, fopg = 32.768 khz, 1.35 v c1 = c2 = 0.1 f, figure 7 [current drain (with the backup flag cleared)] v dd = 3.0 v, halt mode lcd drive method: 1/3 bias | i dd | c1 to c4 = 0.1 f, c1 = 25 k , figure 6 2.0 a co = cg = 20 pf, 32.768 khz xtal lcd drive methods other than v dd = 3.0 v, halt mode 1/3 bias | i dd | c1 = c2 = 0.1 f, ci = 25 k , figure 7 1.0 a co = cg = 20 pf, 32.768 khz xtal oscillator start capacitor | vstt | v dd 1 = v dd , ci = 25 k , figure 4 1.35 v co = cg = 20 pf, 32.768 khz xtal oscillator hold voltage v hold v bak = v dd 1 = v dd /2, ci = 25 k , figures 6 and 7 2.6 v (with the backup flag cleared) co = cg = 20 pf, 32.768 khz xtal oscillator start time tstt v dd 1 = v dd = 1.35 v, ci = 25 k , figure 4 10 sec co = cg = 20 pf, 32.768 khz xtal oscillator correction capacitance 10p xc 8 10 12 pf 20p xtout 16 20 24 pf
no. 5944- 19 /24 lc5824, lc5823, LC5822 ext-v specifications absolute maximum ratings at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max v dd ?.3 +4.0 v v dd 1 ?.3 +4.0 v maximum supply voltage v dd 2 ?.3 +4.0 v v dd 3 (lcd drive method: 1/3 bias) ?.3 +5.5 v v dd 3 (lcd drive methods other than 1/3 bias) ?.3 +4.0 v maximum input voltage s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, v in 2 (with m1 to m4, a1 to a4, and so1 to so4 in input mode) ?.3 v dd + 0.3 v res, tst maximum output voltage m1 to m4, a1 to a4, so1 to so4, (lcd drive method: 1/3 bias) v out 2 (with m1 to m4, a1 to a4, and so1 to so4 in output mode) ?.3 v dd + 0.3 v alm, cup2 v out 3 segout, com1 to com4, cup1 ?.3 v dd 3 + 0.3 v (lcd drive methods other than m1 to m4, a1 to a4, so1 to so4, 1/3 bias) v out 2 (with m1 to m4, a1 to a4, and so1 to so4 in output mode) ?.3 v dd + 0.3 v alm, segout, com1 to com4, cup1 operating temperature topg ?0 +65 c storage temperature tstg ?0 +125 c parameter symbol conditions and applicable pins ratings unit min typ max v dd 1 1.3 3.6 v v dd 2.0 3.6 v supply voltage v dd 2 v dd 3 (lcd drive method: 1/3-bias) 3.9 5.0 v v dd 3 (lcd drive methods other than 1/3 bias) v dd 3 = v dd 2 v s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, high-level input voltage v ih (with m1 to m4, a1 to a4, and so1 to so4 in input mode) v dd ?0.4 v dd v res s1 to s4, k1 to k4, m1 to m4, a1 to a4, so1 to so4, low-level input voltage v il (with m1 to m4, a1 to a4, and so1 to so4 in input mode) 0 0.4 v res operating frequency fopg ta = ?0 + 65 c 32 33 khz allowable operating ranges at ta = 25 c 2 c, v ss = 0 v parameter symbol conditions and applicable pins ratings unit min typ max r in 1a v dd = 3.0 v, v in = 0.35 v dd , low level hold transistor * 1, 50 500 k figure 5 r in 1b v dd = 3.0 v, v in = 0.7 v dd , programmable pull-down 50 1000 k resistor * 1, figure 5 input resistance r in 2a v dd = 3.0 v, v in = 0.35 v dd , input mode, low level hold 50 500 k transistor * 1, figure 5 r in 2b v dd = 3.0 v, v in = 0.7 v dd , input mode, 50 1000 k programmable pull-down resistor * 2, figure 5 r in 3 v dd = 3.0 v, v in = 0.7 v dd /0.3 v dd 10 300 k res pin pull-up/pull-down resistor electrical characteristics at ta = 25 c 2 c, v ss = 0 v, v dd = v dd 2 continued on next page.
no. 5944- 20 /24 lc5824, lc5823, LC5822 continued from preceding page. parameter symbol conditions and applicable pins ratings unit min typ max high-level output voltage v oh 1 v dd = 2.5 v, i oh = ?50 a, alm v dd ?0.65 v low-level output voltage v ol 1 v dd = 2.5 v, i ol = 250 a, alm 0.65 v high-level output voltage v oh 2 v dd = 3.0 v, i oh = ?0 a, m1 to m4, a1 to a4, so1 to so4 v dd ?0.4 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) low-level output voltage v ol 2 v dd = 3.0 v, i ol = 40 a, m1 to m4, a1 to a4, so1 to so4 0.4 v (with m1 to m4, a1 to a4, and so1 to so4 in output mode) segment driver output impedance [when set up as cmos output ports] high-level output voltage v oh 3 v dd = 2.4 v, i oh = ?0 a, segment 1 to 42 v dd ?1 v low-level output voltage v ol 3 v dd = 2.4 v, i ol = 40 a 1 v high-level output voltage v oh 4 v dd = 2.4 v, i oh = ? a, segment 1 to 42 v dd ?1 v low-level output voltage v ol 4 v dd = 2.4 v, i ol = 20 a 1 v [when set up as p-channel open-drain output ports] high-level output voltage v oh 3 v dd = 2.4 v, i oh = ?0 a, segment 1 to 42 v dd ?0.2 0.3 1 v output off leakage current i off v dd = 2.6 v, v ol = v ss 1 a [static drive] high-level output voltage v oh 5 v dd = 3.0 v, i oh = ?.4 a, segout v dd ?0.2 v low-level output voltage v ol 5 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 6 v dd = 3.0 v, i oh = ? a, com1 v dd ?0.2 v low-level output voltage v ol 6 v dd = 3.0 v, i ol = 4 a, com1 0.2 v [duplex drive (1/2 bias - 1/2 duty)] high-level output voltage v oh 5 v dd = 3.0 v, i oh = ?.4 a, segout v dd 2 ?0.2 v low-level output voltage v ol 5 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v high-level output voltage v oh 6 v dd = 3.0 v, i oh = ? a, com1 to com2 v dd 1 ?0.2 v middle-level output voltage v om v dd = 3.0 v i oh = ? a, i ol = 4 a, com1 to com2 v dd 1 + 0.2 v low-level output voltage v ol 6 v dd = 3.0 v, i ol = 4 a, com1 to com2 0.2 v [1/2 bias - 1/3 duty and 1/2 bias - 1/4 duty drive] high-level output voltage v oh 5 v dd = 3.0 v, i oh = ?.4 a, segout v dd ?0.2 v low-level output voltage v ol 5 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v v dd = 3.0 v, i oh = ? a, high-level output voltage v oh 6 com1 to com3 (1/3 duty) v dd 2 ?0.2 v com1 to com4 (1/4 duty) v dd = 3.0 v i oh = ? a, i ol = 4 a, middle-level output voltage v om com1 to com3 (1/3 duty) v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com4 (1/4 duty) v dd = 3.0 v, i ol = 4 a, low-level output voltage v ol 6 com1 to com3 (1/3 duty) 0.2 v com1 to com4 (1/4 duty) continued on next page.
no. 5944- 21 /24 lc5824, lc5823, LC5822 continued from preceding page. parameter symbol conditions and applicable pins ratings unit min typ max [1/3 bias - 1/3 duty and 1/3 bias - 1/4 duty drive] high-level output voltage v oh 5 v dd = 3.0 v, i oh = ?.4 a, segout v dd 3 + 0.2 v middle-level output voltage v om 1? v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 2 ?0.2 v dd 2 + 0.2 v v om 2? v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, segout v dd 1 ?0.2 v dd 1 + 0.2 v low-level output voltage v ol 5 v dd = 3.0 v, i ol = 0.4 a, segout 0.2 v v dd = 3.0 v, i oh = ?.4 a, high-level output voltage v oh 6 com1 to com3 (in 1/3 duty mode) v dd 3 + 0.2 v com1 to com4 (in 1/4 duty mode) v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, v om 1? com1 to com3 (in 1/3 duty mode) v dd 2 ?0.2 v dd 2 + 0.2 v com1 to com4 (in 1/4 duty mode) middle-level output voltage v dd = 3.0 v, i oh = ?.4 a, i ol = 0.4 a, v om 2? com1 to com3 (in 1/3 duty mode) v dd 1 ?0.2 v dd 1 + 0.2 v com1 to com4 (in 1/4 duty mode) low-level output voltage v ol 6 v dd = 3.0 v, i ol = 0.4 a 0.2 v [output voltage] lcd drive method: 1/3 bias (halver) v dd 1 v dd = 3.0 v, fopg = 32.768 khz, 1.35 v c1 to c4 = 0.1 f, figure 6 (tripler) v dd 3 v dd = 3.0 v, fopg = 32.768 khz, 4.1 v c1 to c4 = 0.1 f, figure 6 lcd drive method: 1/2 bias (halver) v dd 1 v dd = 3.0 v, fopg 32.768 khz, c1 = c2 = 0.1 f, figure 7 1.35 v [current drain (with the backup flag cleared)] lcd drive method: 1/3 bias | i dd | v dd = 3.0 v, halt mode, c1 to c4 = 0.1 f, ci = 25 k 5.0 a co = cg = 20 pf, 32.768 khz xtal, figure 6 lcd drive methods other than | i dd | v dd = 3.0 v, halt mode, c1 to c2 = 0.1 f, ci = 25 k , 5.0 a 1/3 bias figure 7, co = cg = 20 pf, 32.768 khz, xtal oscillator start voltage vstt v dd = v dd 2, ci = 25 k , figure 4, 2.2 v co = cg = 20 pf, 32.768 khz xtal oscillator hold voltage v hold v dd = v dd 2, ci = 25 k , , figures 5, 6, 7, and 8, 2.0 v (with the backup flag cleared) co = cg = 20 pf, 32.768 khz xtal oscillator start time tstt v dd = v dd 2 = 2.2 v, ci = 25 k , figure 4 10 sec co = cg = 20 pf, 32.768 khz xtal oscillator correction capacitance 10p xc 8 10 12 pf 20p xtout 16 20 24 pf note : 1. s1 to 4, k1 to 4 2. m1 to 4, a1 to 4, so1 to 4
figure 1 s1 to s4, k1 to k4, m1 to m4, a1 to a4, and so1 to so4 can be applied by application software no. 5944- 22 /24 lc5824, lc5823, LC5822 figure 2 output voltage, current drain, and oscillator hold voltage test circuit figure 3 output voltage, current drain, and oscillator hold voltage test circuit
no. 5944- 23 /24 lc5824, lc5823, LC5822 figure 4 oscillator start voltage, oscillator start time, and frequency stability test circuit figure 5 s1 to s4, k1 to k4, m1 to m4, a1 to a4, and so1 to so4 can be applied by application software figure 6 output voltage, current drain, and oscillator hold voltage test circuit
this catalog provides information as of august, 1998. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any and all sanyo products described or contained herein fall under strategic products (including services) controlled under the foreign exchange and foreign trade control law of japan, such products must not be exported without obtaining export license from the ministry of international trade and industry in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. ps no. 5944- 24 /24 lc5824, lc5823, LC5822 figure 7 output voltage, current drain, and oscillator hold voltage test circuit figure 8 output voltage, current drain, and oscillator hold voltage test circuit

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